A processor of a computing system may be interconnected with various other components of the system such as, for example, memory and I/O units. An interconnect between the processor and other system components may include one or more data links, each including a number of lanes.
In some computing systems, high-speed data links may tend to draw significant amounts of system power. To reduce power consumption, some solutions include modulating link width by switching off data bit lines based on link utilization. While this method may be effective in addressing the average behavior of data traffic, link usage must be monitored across a time interval to converge on average values, which may result in the link losing the opportunity to react to traffic fluctuations. As a result of residing too long in one width, the system may experience either higher power or higher latency.
In addition, using utilization to decide the link width may not be scalable as far as performance and latency is concerned. For example, in a processor with 10 cores, but with only one out of 10 cores currently active, the overall bandwidth and utilization of the link may be very low. A strictly utilization/bandwidth-based width control would make the link width lowest possible. If the one active core needs extensive accesses over the link then as compared to full width, the latency, and thus, performance of that core may tend to degrade.
all in accordance with embodiments of the present disclosure.